W83L786R/ W83L786G
Publication Release Date: March 06
  - 30 -
Revision0.8
Power on default [7:0] = 000P, PPPP b (P: power on trapping)
BIT
NAME
READ/WRITE
DESCRIPTION
7-5
Reserved
Read Only     Reserved.
4     VID4P_VAL
Read Only    VID4 Value. Reading this bit will return the value of pin 5.
3     VID3P_VAL
Read Only     VID3 Value. Reading this bit will return the value of pin 4.
2     VID2P_VAL
Read Only     VID2 Value. Reading this bit will return the value of pin 3.
1     VID1P_VAL
Read Only     VID1 Value. Reading this bit will return the value of pin 2.
0     VID0P_VAL
Read Only     VID0 Value. Reading this bit will return the value of pin 1.
8.17 VID0-4/GPIO1-5 Output Mode Control Register - Index 50h
Power on default [7:0] = 0000, 0000 b
BIT
NAME
READ/WRITE
DESCRIPTION
7-5
Reserved
Read/write     Reserved.
4
VID4_OB
Read/write
Enable VID4/GPIO5 as Output Buffer. Set to
<1> VID4/GPIO5 can drive logical high or logical low.
<0> VID4/GPIO5 is open-drain.
3
VID3_OB
Read/write
Enable VID3/GPIO4 as Output Buffer. Set to
<1> VID3/GPIO4 can drive logical high or logical low.
<0> VID3/GPIO4 is open-drain.
2
VID2_OB
Read/write
Enable VID2/GPIO3 as Output Buffer. Set to
<1> VID2/GPIO3 can drive logical high or logical low.
<0> VID2/GPIO3 is open-drain.
1
VID1_OB
Read/write
Enable VID1/GPIO2 as Output Buffer. Set to
<1> VID1/GPIO2 can drive logical high or logical low.
<0> VID1/GPIO2 is open-drain.
0
VID0_OB
Read/write
Enable VID0/GPIO1 as Output Buffer. Set to
<1> VID0/GPIO1 can drive logical high or logical low.
<0> VID0/GPIO1 is open-drain.
 
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